STAN AND BURLESON : LOW - POWER DRIVERS 151 GND Vin Vout C = 1 nF Vdd / 2 Vdd Vdd INn

| The clock tree of modern synchronous VLSI circuits can consume as much as 50% of their entire power budget. Diierent methods of decreasing clock power dis-sipation have been proposed based on low-voltage swings, double-edge triggered ip-ops, gated clocks, etc. In this paper we propose two types of full-swing low-power CMOS clock drivers. Both are based on a stepped charging and discharging of the clock tree capacitance in order to achieve up to 50% power savings. The rst CMOS driver targets single-phase clocking schemes and is based on a quantized adiabatic operation that uses two power supply voltages (V dd and V dd=2, V dd=2 can be replaced by a tank capacitor). The second CMOS driver proposed targets dual-phase clocking schemes and achieves low-power operation by charge reuse. The proposed circuits are more than twice larger and slightly slower than standard inverter-chain clock drivers. In this way the circuits present the designer with the usual trade-oos area, speed vs. power dissipation. The theoretical power savings of 50% compared with the inverter-chain driver are smaller for actual circuits (around 25-30% depending on the capacitive load). The two-step charging and discharging used by both drivers proposed in this paper introduce small discontinu-ities on the signal edges and for this reason they are not suitable for clocking schemes that are extremely critical to clock transition times. The proposed low-power CMOS drivers can be used for oo-chip or on-chip clock transmission for highly pipelined circuits, systolic arrays, wafer-scale integration synchronous circuits or as I/O drivers for heavily loaded buses whenever low-power operation with full voltage swing is desired and absolute maximum speed is not a must. Keywords| CMOS clock driver, adiabatic operation, charge recovery, low-power.